1. Field of the Invention
The present invention relates to a solid-state imaging device, an imaging apparatus, and a method for manufacturing the solid-state imaging device. Further, the present invention relates to a substrate and, more specifically, a substrate having a number of electrodes formed to protrude on a base, and a semiconductor device using the substrate.
Priority is claimed on Japanese Patent Application No. 2012-006986, filed on Jan. 17, 2012, Japanese Patent Application No. 2012-079215, filed on Mar. 30, 2012, and Japanese Patent Application No. 2012-081930, filed on Mar. 30, 2012, the content of which is incorporated herein by references.
2. Description of Related Art
In recent years, video cameras, electronic still cameras, and the like have been widely popularized. A CCD (Charge Coupled Device)-type or amplification-type solid-state imaging device is used for such a camera. The amplification-type solid-state imaging device guides signal charges generated and accumulated by a photoelectric conversion unit of a pixel on which light is incident to an amplification unit provided in the pixel, and outputs the signal amplified by the amplification unit from the pixel. In the amplification-type solid-state imaging device, a plurality of pixels are arranged in a two-dimensional matrix. An example of the amplification-type solid-state imaging device includes a CMOS (Complementary Metal Oxide Semiconductor)-type solid-state imaging device using CMOS transistors.
In related art, a general CMOS-type solid-state imaging device adopts a scheme of sequentially reading, for each row, signal charges generated by photoelectric conversion units of the respective pixels arranged in a two-dimensional matrix. In this scheme, since a timing of exposure in the photoelectric conversion unit of each pixel is determined by start and end of readout of signal charges, the exposure timing differs for each row.
Further, uses of a CMOS-type solid-state imaging device having a global shutter function are increasing. In the CMOS-type solid-state imaging device having the global shutter function, signal charges generated by photoelectric conversion units are normally accumulated until readout is performed. For this reason, it is necessary to have accumulation capacitors having a light shielding property. In such a CMOS solid-state imaging device of the related art, all pixels are simultaneously exposed, and then signal charges generated by respective photoelectric conversion units are simultaneously transferred to the respective accumulation capacitors in all the pixels and temporarily accumulated. The signal charges are sequentially converted into pixel signals and read at a predetermined readout timing.
A solid-state imaging device in which a MOS image sensor chip in which micropads are formed on the side of a wiring layer in each unit cell and a signal processing chip in which micropads are formed on the side of the wiring layer in positions corresponding to the micropads of the MOS image sensor chip are connected by microbumps is disclosed in Japanese Patent Laid-Open Publication No. 2006-49361. Further, a method of preventing an increase in a chip area using a solid-state imaging device in which a first substrate having photoelectric conversion units formed therein and a second substrate having a plurality of MOS transistors formed therein are bonded is disclosed in Japanese Patent Laid-Open Publication No. 2010-219339.
A semiconductor device having a three-dimensional structure has attracted attention as a powerful structure to avoid various barriers faced by a semiconductor device having a two-dimensional structure, such as limits of lithography technology in miniaturization, an increase in wiring resistance or parasitic effects due to miniaturized wirings and an increased wiring length, a saturation tendency of an operating speed associated with the increase, or a high electric field effect due to miniaturized element dimensions, and to maintain an improved degree of integration, by three-dimensionally integrating a semiconductor element with a structure in which a number of semiconductor active layers are stacked.
For manufacture of the semiconductor device having a three-dimensional structure, a stacked semiconductor device formed by bonding wafers having a number of very small electrodes formed therein has been studied.
In such a stacked semiconductor device, formation of protrusion electrodes of a conductive material and dummy protrusion units having a greater height than the protrusion electrodes (hereinafter referred to as “dummy electrodes”) on wafers and definition of a gap between the wafers using the projection units is disclosed in Japanese Patent Laid-Open Publication No. 2007-281393. Accordingly, a predetermined gap is accurately held by an electrical insulating material attached to a surface of an electronic part in an inner region of the protrusion unit.